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Add ' to keywords for systemverilog This makes values like 8'hbb match as a single word when moving
author zegervdv <zegervdv@me.com>
date Fri, 05 Mar 2021 18:19:42 +0100
parents d726921aaabe
children
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" Define some common typos

Abolish  teh                                the
Abolish  hte                                the
Abolish  {leng,wid,bandwid,streng}ht        {}th
Abolish  {heig}th                           {}ht
Abolish  por{ject,gram}                     pro{}
Abolish  {,as,de,re}sing{,s,ed}             {}sign{}
Abolish  {std_,}loigc{,_vector}             {}logic{}
Abolish  emtpy                              empty


" Code typos
Abolish rpsec rspec