comparison dot_config/helix/runtime/queries/verilog/indents.scm @ 878:837fdac1f972 draft

feat: add some verilog indent options
author Zeger Van de Vannet <zeger@vandevan.net>
date Wed, 17 Apr 2024 08:08:21 +0200
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877:56e26ce1a5ce 878:837fdac1f972
1 [
2 (module_declaration)
3 (seq_block)
4 ] @indent
5
6 [
7 "end"
8 "endmodule"
9 ] @outdent