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changeset 878:837fdac1f972 draft

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feat: add some verilog indent options
author Zeger Van de Vannet <zeger@vandevan.net>
date Wed, 17 Apr 2024 08:08:21 +0200
parents 56e26ce1a5ce
children 0a7f9b99faab
files dot_config/helix/runtime/queries/verilog/indents.scm
diffstat 1 files changed, 9 insertions(+), 0 deletions(-) [+]
line wrap: on
line diff
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/dot_config/helix/runtime/queries/verilog/indents.scm	Wed Apr 17 08:08:21 2024 +0200
@@ -0,0 +1,9 @@
+[
+ (module_declaration)
+ (seq_block)
+] @indent
+
+[ 
+  "end"
+  "endmodule"
+] @outdent